At the moment, the Intel Foundry Know-how Analysis workforce introduced expertise breakthroughs in 2D transistor expertise utilizing beyond-silicon supplies, chip interconnects, and packaging expertise, amongst others. The corporate will unveil its analysis in seven of its personal papers, together with two extra papers in collaboration with trade companions like imec, on the IEEE Worldwide Electron Units Assembly (IEDM) 2024 convention.
Intel’s disclosures embrace new analysis that enhances gate-all-around (GAA) transistor scaling and efficiency each with silicon and with atomically-thin 2D transistors that use beyond-silicon supplies. Intel additionally outlined its subtractive Ruthenium expertise that improves interconnect efficiency and scalability, in the end enabling smaller wires between transistors, and a chip packaging breakthrough that improves chip-to-chip meeting throughput by 100x.
Intel’s Know-how Analysis workforce, previously often known as the Elements Analysis workforce for the final 50 years, is a part of Intel Foundry. This workforce works on growing merchandise supposed for commercialization within the nearer time period than the extra far-looking initiatives at Intel Labs. The Know-how Analysis workforce is thought for paving the best way for a lot of of Intel’s basic applied sciences, with the newest improvements just like the PowerVia bottom energy supply and RibbonFET gate-all-around structure originating on this group.
Intel hasn’t offered the papers at IEDM but, and our one-on-one dialogue with the Basic Supervisor of the Analysis Workforce isn’t till tomorrow. We’ll present the descriptions of the breakthroughs beneath, however we’ll circle again with an replace to fill in additional particulars.
Interconnect scaling breakthough
As transistors get smaller, so too should the wires (interconnects) that join them. Copper is the fabric of alternative for the billions of nanometer-scale wires that transfer energy and information round contained in the chip in a fancy 3D grid (you’ll be able to see what this looks like in this video). In actual fact, as much as 50 miles of interconnect wiring are inside trendy chips. Nonetheless, the power to shrink these microscopic wires is working out of steam, and most alternate options aren’t appropriate for high-volume manufacturing. This can be a crucial roadblock to transferring ahead to smaller course of nodes.
Very like a typical copper wire you utilize in your house for electrical gadgets, the wires that carry electrons between transistors want an insulator, on this case, a dielectric coating, to forestall the electrons from going locations they shouldn’t. Nonetheless, the wires additionally require a barrier to forestall copper diffusion that might contaminate the dielectric. This barrier creates points with shrinking the wires.
Shrinking the interconnect wires in a processor is exceedingly troublesome due to the necessities of copper damascene, an additive course of used to create the wires. First, a trench is created, then a barrier is deposited within the trench on high of a dielectric. A seed layer is then positioned on high of the barrier to allow copper electroplating; then, copper is deposited on high. Any extra materials on the high is then polished away.
As proven within the picture above, reducing the quantity of copper helps to skinny the wire, but it surely additionally decreases the ratio of the copper (bulk) to the barrier and seed layer, and resistivity will increase exponentially because the wires are shrunk. This implies the wires carry much less present, slowing the system velocity (amongst different results) and impacting capacitance.
Intel’s Know-how Analysis workforce has developed a course of appropriate for high-volume manufacturing that makes use of Ruthenium as a substitute of copper. It additionally options air gaps.
Air gaps are a expertise that Intel launched again within the 14nm course of node. This system removes sections of the insulative dielectric, leaving air as a substitute (air has a dielectric fixed of round 1.0) to scale back capacitance (Intel claimed a 17% enchancment in capacitance with 14nm).
Intel hasn’t shared the deep dive particulars of its Subtractive Ruthenium course of, however we’re positive to study extra particulars through the presentation. Intel says its Subtractive Ruthenium course of with airgaps supplies as much as 25% capacitance at matched resistance at sub-25nm pitches (the center-to-center distance between interconnect traces). Intel says its analysis workforce “was first to display, in R&D check automobiles, a sensible, cost-efficient and high-volume manufacturing suitable subtractive Ru built-in course of with airgaps that doesn’t require costly lithographic airgap exclusion zones round vias, or self-aligned through flows that require selective etches.”
Intel envisions utilizing this method for probably the most crucial layers with the smallest pitches at first, whereas customary copper damascene will probably be used for the bigger higher layers. Naturally, Rutheniuem may even be helpful for its PowerVia bottom energy supply. Ultimately, these smaller wires will allow connecting to smaller transistors, and Intel says this tech will probably be utilized in future Intel Foundry nodes.
Gate-All-Round (GAA) transistor breakthroughs
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Intel’s RibbonFET is its first new transistor design since FinFET arrived greater than 13 years in the past. It’s Intel’s first gate-all-around (GAA) transistor, debuting with the 20A and 18A nodes. It options stacked nanosheets surrounded completely by a gate, versus the fins surrounded on three sides used for FinFET.
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Now, the problem is to shrink the GAA designs additional, and Intel is tackling that in each customary silicon designs and utilizing new 2D supplies. With customary silicon, Intel’s transistor disclosures present enhanced gate-all-around RibbonFET CMOS scaling, leading to a gate size of 6nm and a nanoribbon/nanosheet thickness of 1.7nm whereas delivering improved quick channel results and better efficiency.
On the primary facet, the gate size vs electron velocity graph on the best reveals a powerful profile. The desk within the heart of the slide reveals comparisons to present transistor applied sciences, with the Tfin/Tsi (fin thickness/nanoribbon thickness) for the nanoribbon being almost twice as skinny because the fin utilized in FinFET.
The most important query is, what’s subsequent after silicon? After CFET transistors arrive, the subsequent step of GAA is to vary the supplies utilized in NMOS and PMOS transistors to 2D supplies (just a few atoms thick). The second slide outlines Intel’s advances utilizing atomically skinny transition-metal dichalcogenide (TMD) supplies, broadly regarded as the supplies used after silicon.
Intel fabricated 2D gate-all-around NMOS and PMOS transistors with a gate size of 30nm utilizing moly-based materials. Intel claims this effort delivered ‘finest at school NMOS drive currents,’ a 2X enchancment over the next-best revealed consequence. The chart on the best reveals the analysis car outperforming different such exploratory efforts into TMDs.
Intel’s transistor observe additionally features a view again on the final 60 years of transistor tech and a name to motion for the trade to develop transistors that function at ultra-low Vdd (provide voltages) of sub-300mV, a considerable lower from right now’s 1V vary. This can be a stretch aim for the 2030s and 2040s.
Packaging breakthroughs
Intel’s new Selective Layer Switch (SLT) tech allows attaching a complete wafer of chip dies to a different wafer at extraordinarily excessive speeds —Intel says SLT allows a 100X enhance in throughput for the chip-to-chip meeting course of. With SLT, all the wafer filled with dies could be related to the underlying wafer without delay, and particular person dies could be chosen for bonding whereas others could be excluded. This tech makes use of inorganic infrared laser debonding.
Intel additionally cites that SLT “allows ultra-thin chiplets with significantly better flexibility to allow smaller die sizes and better facet ratios versus conventional chip-to-wafer bonding.” Intel’s descriptions of this new tech aren’t completely clear, so we hope to study extra from the presentation. It seems this could be a terrific various to approaches that use reconstituted wafers. We’ll add extra element right here as soon as we study extra.
Intel may even have an IEDM-invited discuss tomorrow’s packaging options. This slide above revealed EMIB-T, which hasn’t been disclosed beforehand. As a reminder, EMIB is Intel’s Embedded Multi-Die Interconnect Bridge, a low-latency, low-power, and high-bandwidth interconnect that connects die collectively.
Intel disclosed that EMIB-T stands for EMIB-TSV. This variant marks the primary EMIB implementation that makes use of TSVs to ship the sign by the bridge with TSVs as a substitute of wrapping the sign across the bridge.
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At IEDM, Intel will submit seven papers together with two different papers with companions reminiscent of imec, Aixtron, and the Tor Vergata College of Rome.
We have now time carved out with Intel for follow-up questions, and we’ll replace this piece with extra particulars quickly.
